- Home
- Staff
- Teaching
- Research
- Formal Verification of Analog AI Hardware (FAI)
- Energy Optimised Analog Circuits for Deep Neural Networks (ENERGICS)
- Formal Abstraction and Verifcation of Analog Circuits (faveAC)
- Analog-Coverage in der Nanoelektronik (ANCONA)
- Hochverlässliches selbst-adaptives Mixed-Signal Multi-Core System-on-Chip(MixedCoreSoC)
- Mikrosystem-Design-Flow für KMUs (MiDes)
- Code-Coverage for Verilog-A Models
- ASDeX (Formalized Specification of Analog Circuits)
- FAC'14 Benchmark Suite
- Equivalence Checking (Vera) Simulation (gnucap-uf)
- Joint Robotics Lab
- Downloads
- Cadence Academic Network
- Studentische Projekte
- List of Publications
- Thesis
- Internal
Yasmin Abu-Haeyeh
Postal address:
Yasmin Abu-Haeyeh
Professur für Entwurfsmethodik
Institut für Informatik
Johann Wolfgang Goethe-Universität
Postfach 11 19 32
60054 Frankfurt am Main
Phone:
+49 69 798-28242
eMail:
abu-Haeyeh(at)em.uni-frankfurt.de
Office:
Room 213
Rob.Mayer-Str. 11-15
60325 Frankfurt
