Konferenzbeiträge

2017

  • Philipp Tertel, Lars Hedrich: "Real-Time Emulation of Block-Based Analog Circuits on an FPGA", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) ,Taormina, Italy, June 2017
  • Andreas Fürtig, Moritz Paschke, Lars Hedrich: "Comparing Code Coverage Metrics for Analog Behavioral Models", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) ,Taormina, Italy, June 2017
  • Georg Glaser, Martin Grabmann, Gerrit Kropp and Andreas Furtig: "Automated Generation of System-Level AMS Operating Condition Checks: Your Model's Insurance Policy", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) ,Taormina, Italy, June 2017
  • Andreas Fürtig, Georg Gläser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee,Gregor Nitsche, Markus Olbrich, Carna Radojicic, and Fabian Speicher, “Novel Metrics for Analog Mixed-Signal Coverage”, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Dresden, April 2017

2016

  • Andreas Fürtig, Sebastian Steinhorst, Lars Hedrich: "Feature based State Space Coverage of Analog Circuits". In: Proceedings of the Forum on Specification and Design Languages (FDL 2016). Germany, pdf
  • Erich Barke, Andreas Fürtig, Georg Gläser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic and Fabian Speicher : "Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis",  2016 Design, Automation & Test in Europe Conference (DATE), pp. 1102--1111, 2016, pdf

2015

  • A. Fürtig: "Detecting Design Flaws using Analog State Space Coverage", FDL 2015, Forum on specification & Design Languages, Barcelona, Special Session "Towards Analog-/Mixed-Signal Coverage"
  • Felix Salfelder and Lars Hedrich, "Ageing Simulation of Analogue Circuits and Systems Using Adaptive Transient Evaluation", Proceedings of IEEE/ACM Conference on Design, Automation and Test in Europe (DATE'15), March 9-13 2015, Grenoble, France. pdf
  • Dackermann, Tim, Rolando Doelling, and Lars Hedrich. "Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains." Systems Engineering (ISSE), 2015 IEEE International Symposium on. IEEE, 2015.
  • Julius von Rosen, Markus Meissner and Lars Hedrich, "Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores", Proceedings of IEEE/ACM Conference on Design, Automation and Test in Europe (DATE'15), March 9-13 2015, Grenoble, France. pdf
  • Dackermann, Tim, Miller, Steve, Hedrich, Lars and Doelling, Rolando :"Flexible Gear Model Library - Vibration Excitation Mechanisms and Gear Force Calculation",  Proceedings of the IASTED International Conference
    Modelling, Identification and Control (MIC 2015) , 2015, Innsbruck, Austria
  • Julius von Rosen and Lars Hedrich, "Mixed-Signal Multi-Core Circuit Architecture for a Reliable Task Distribution", 8. GMM/ITG/GI-Fachtagung für Zuverlässigkeit und Entwurf - ZuE 2015, Siegen, Deutschland, 21.- 23. September 2015

2014

  • Felix Salfelder and Lars Hedrich, "Evaluation of a Benchmark Suite for Formal Verification of Analog Circuits", International Workshop on Design Automation for Analog and Mixed-Signal Circuits at ICCAD '14, 2014, San Francisco, USA, Slides
  • T. Shumate, J. von Rosen, L. Hedrich: "A Highly Dependable Reactive Architecture Layer for Autonomous Robots based on an Artificial Analog Hormone System", Analog '14: 14. ITG/GMM-Fachtagung Entwicklung von Analogschaltungen mit CAE-Methoden, Aachen, Germany
  • Felix Salfelder and Lars Hedrich, "A Benchmark Suite for Formal Verification of Analog Circuits", FAC '14: Frontiers in Analog Computer Aided Design, 2014, Grenoble, France
  • I. Gradek, K. Hahn, H. Kremer, L. Hedrich, F. Salfelder,  W.Korb, F. Völklein, R. Brück: "MiDes – Mikrosystemtechnik-Design-Flow für KMU", edaWorkshop 14, May 13-14, 2014, Hannover, Germany  

2013

  • L.Hedrich, M.Meissner: "FAATS, a Fully Automated Analog Topology Synthesis Framework", DASS 2013, Dresdner Arbeitstagung Schaltungs- und Systementwurf , Dresden, Germany 
  • M. Kauer, S. Naranayaswami, S. Steinhorst, M. Lukasiewycz, S. Chakraborty, L. Hedrich. "Modular system-level architecture for concurrent cell balancing" In Proceedings of the 50th Annual Design Automation Conference (DAC '13), 2013
  • F. Salfelder, L. Hedrich, M. Meissner: "Evaluating NBTI in Synthesized Operational Amplifiers using an Accurate Ageing Model", Analog '13: 13. ITG/GMM-Fachtagung Entwicklung von Analogschaltungen mit CAE-Methoden, Aachen, Germany 
  • Lars Hedrich Benjamin Betting, Julius von Rosen and Uwe Brinkschulte: "A Highly Dependable Self-Adaptive Mixed-Signal Multi-Core System-on-Chip", In 26th International Conference on Architecture of Computing Systems (ARCS 2013), Prague, Czech Republic, February 19th - 22nd 2013.
  • M. Ma, L. Hedrich, S. Steinhorst: "ASDeX-driven Analog Circuit Verification" (Abstract), Frontiers in Analog CAD (FAC'13), A Satellite Workshop of the International Solid-State Circuits Conference (ISSCC'13), Berkley, CA, USA, Feb. 14-15th, 2013

2012

  • B. Betting, J. v. Rosen, L. Hedrich, U. Brinkschulte: "A Highly Dependable Self-Adaptive Mixed-Signal Multi-Core System-on-Chip",26th International Conference on Architecture of Computing Systems (ARCS 2013), February 19th - 22nd 2013, Prague, Czech Republic 
  • J. v. Rosen: "A Highly Dependable, Analog Artificial Hormone System as Middleware for a Multi-Core System-on-Chip", PhD Forum, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '12), October 7-10, 2012, Santa Cruz, USA 
  • M. Ma, M. Meissner, L. Hedrich: "A Case Study: Automatic Topology Synthesis for Analog Circuit from an ASDeX Specification", In proceedings of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2012 (SMACD'12), Seville, Spain, 19-21 September 2012 
  • J. v. Rosen, B. Betting, U. Brinkschulte, L. Hedrich: "Ein hochverlässliches, selbst-adaptives, Mixed-Signal Mehrkern-System-on-Chip", 6. GMM/GI/ITG-Fachtagung für Zuverlässigkeit und Entwurf - ZuE 2012, Bremen, Deutschland, 25.- 27. September 2012 
  • S. Steinhorst, L. Hedrich. “Trajectory-Directed Discrete State Space Modeling for Formal Verification of Nonlinear Analog Circuits”, In ICCAD’12: Proceedings of the 2012 International Conference on Computer-Aided Design, San Jose, USA, November 2012.
  • S. Steinhorst, L. Hedrich. “Equivalence Checking of Nonlinear Analog Circuits for Hierarchical AMS System Verification”, Proc. of the IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, USA, October 2012. 
  • S. Steinhorst, L. Hedrich. “Analog Assertion-Based Verification on Partial State Space Representations using ASL”, Proc. of the Forum on specification and Design Languages (FDL) 2012, Vienna, Austria, September 2012.
  • M. Barke, M. Kärgel, W. Lu, F. Salfelder, L. Hedrich, M. Olbrich, M. Radetzki, U. Schlichtmann. "Robust Validation of Integrated Circuits and Systems", 4th Asia Symposion on Quality Electronic Design (ASQED) 2012, Penang, Malaysia, July 2012
  • K. Hahn, L. Hedrich, F. Salfelder, H. Kremer, F. Völklein, W.Korb: "MiDes - Mikrosystemtechnik Design Flow für KMU", edaWorkshop 12, May 8-9, 2012, Hannover, Germany. 
  • Chr. Leineweber, M. Pacher, B. Betting, J. v. Rosen, U. Brinkschulte, L. Hedrich: ”Detection and Defense Strategies Against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip”, Proceedings of The 15th IEEE International Symposium on Object/component/service-oriented Real-time distributed computing - ISORC 2012, Shenzen, China, April 11-13, 2012 
  • M. Meissner, O. Mitea, L. Luy, L. Hedrich: "Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework", Proceedings of IEEE /ACM Conference on Design, Automation and Test in Europe (DATE'12), March 12-16, 2012, Dresden Germany. 
  • O. Mitea: "A Deterministic Automatic Flow for the Synthesis of Analog Circuits", PhD Forum, IEEE /ACM Conference on Design, Automation and Test in Europe (DATE'12), March 12-16, 2012, Dresden Germany.

2011

  • M. Meissner, O. Mitea, L. Hedrich: "Graphen-basiertes Framework zur explorativen Topologiesynthese von analogen Schaltungen", ANALOG 2011: Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 12. ITG/GMM-Fachtagung, Erlangen, Germany, 07.- 09. November 2011. 
  • Salfelder, F. & Hedrich, L. An NBTI model for efficient transient simulation of analogue circuits Proc. edaWorkshop 11, VDE Verlag, 2011, p27 - 32 PDF 
  • O. Mitea, M. Meissner and L. Hedrich: "Topology Synthesis of Analog Circuits with Yield Optimization and Evaluation using Pareto Fronts", 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 3–5, 2011, Hong Kong, China. 
  • M. Ma, L. Hedrich, Ch. Sporrer: "A Machine-Readable Specification of Analog Circuits for Integration into A Validation Flow", Proceedings of conference on the Forum for Design Languages (FDL 2011), Oldenburg, Germany, 13-15 September 2011. 
  • M. Meissner, O. Mitea and L. Hedrich: "Graph-based Framework for Explorative Topology Synthesis of Analog Circuits" (Abstract), Frontiers in Analog Circuit Synthesis and Verification (FAC'11), A Satellite Workshop of the 23rd International Conference on Computer Aided Verification (CAV'11), Snowbird, Utah, USA, 14.+15. July 2011. 
  • O. Mitea, M. Meissner, L. Hedrich, P. Jores: "Automated Constraint-driven Topology Synthesis for Analog Circuits" Proceedings of IEEE /ACM Conference on Design, Automation and Test in Europe (DATE'11), Grenoble, France, 14-18 March, 2011. 
  • J. Henkel, L. Bauer, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig, L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U. Schlichtmann, O. Spinczyk, M. Tahoori, J. Teich, N. Wehn, H.-J. Wunderlich: Design and architectures for dependable embedded systems. Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, pages 69-78, 2011 
  • M. Barke, D. Helms, M. Kärgel, W. Lu, F. Salfelder, B. Sander, V. Schöber, „ROBUST – Entwurf Robuster Nanoelektronischer Systeme“, Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen 2011, Passau, Germany

2010

  • M. Radetzki, O. Bringmann, W. Nebel, M. Olbrich, F. Salfelder, U. Schlichtmann, "Robustheit nanoelektronischer Schaltungen und Systeme", ZuE: Zuverlässigkeit und Entwurf - 4. GMM/GI/ITG-Fachtagung, September 2010 
  • S. Steinhorst, L. Hedrich. "Improving Verification Coverage of Analog Circuit Blocks by State Space-Guided Transient Simulation", Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS'10), Paris, France, pp.645-648, June 2010. [BIB
  • O. Mitea, M. Heinz, L. Hedrich: "Ausbeuteoptimierung für die automatische Topologiesynthese von analogen integrierten Schaltungen." ANALOG 2010: Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 11. ITG/GMM-Fachtagung, pages 21-26, Erfurt, Germany, March 2010. 
  • St. Lämmermann, J. Ruf, Th. Kropf, W. Rosenstiel, A. Viehl, A. Jesser, L. Hedrich: Towards assertion-based verification of heterogeneous system designs. Proceedings of IEEE /ACM Conference on Design, Automation and Test in Europe (DATE'10), Dresden, pages 1171-1176, March 2010.

2009

  • S. Steinhorst, L. Hedrich. "Joint Property Specification for Transient Simulation and Formal Verification of Analog Circuits", Proc. of the edaWorkshop'09, Dresden, Germany, pp.13-18, May 2009. 
  • S. Steinhorst, M. Peter, L. Hedrich. "State Space Exploration of Analog Circuits by Visualized Multi-Parallel Particle Simulation", Proc. of the 2009 Int. Conf. on Signal Processing Systems, Singapore, pp.858-862, May 2009. 
  • E. Barke, D. Grabowski, H. Graeb, L. Hedrich, S. Heinen, R. Popp, S. Steinhorst, Y. Wang. "Formal Approaches to Analog Circuit Verification", Proc. of the Conference on Design, Automation and Test in Europe 2009 (DATE'09), Nice, France, pp.724-729, April 2009. 
  • S. Lämmermann, A. Jesser, R. Weiss, J. Ruf, L. Hedrich, T. Kropf, W. Rosenstiel. "An Assertion-Based Verification Methodology for SystemC-AMS Designs", The 15th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'09), Okinawa, Japan, pp. 434-439, März 2009.

2008

  • S. Lämmermann, A. Pacholik, A. Jesser, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Improving Mixed-Signal Verification by Assertion Based Design", The 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'08), Rhodos, Griechenland, pp. 144-147, Oktober 2008. 
  • O. Ohlendorf, S. Steinhorst, W. Hartong, L. Hedrich. "Comparing Two Analog Waveforms - A Trivial Task?", ZuE'08 (2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf), pp. 153-154, September 2008. 
  • S. Steinhorst, L. Hedrich. "A Formal Approach to Complete State Space-Covering Input Stimuli Generation for Verification of Analog Systems", Analog'08 (10. ITG/GMM-Fachtagung), pp. 57-62, April 2008. 
  • S. Steinhorst, L. Hedrich, "Model Checking of Analog Systems using an Analog Specification Language", Proc. of the Conference on Design, Automation and Test in Europe 2008 (DATE'08), pp.324-329, March 2008. 
  • X. Wang, L. Hedrich, "Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology", Proc. of the Conference on Design, Automation and Test in Europe (DATE), Mar. 2008 
  • A. Jesser, L. Hedrich. "A Symbolic Approach for Mixed-Signal Model Checking", The 13th Asia and South Pacific Design Automation Conference (ASP-DAC'08), COEX, Seoul, Korea, pp. 404-409, January 2008

2007

  • X. Wang, L. Hedrich, "Hierarchical Symbolic Analysis of Analog Circuits Using Two-Port Networks", Proc. of 6th WSEAS international conference on circuits, systems, electronics, control and signal processing (CSECS), Dec. 2007. 
  • A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Analog Simulation Meets Digital Verification - A Formal Assertion Approach for Mixed-Signal Verification", The 14th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'07), Sapporo, Japan, pp. 507 - 514, Oktober 2007 
  • Chr. Grimm, R. Jancke, L. Hedrich, S. Huss, H. Gräb: "Struktursynthese von Analogen und Mixed-Signal Schaltungen: Schwarze Magie?", Proceedings Edaworkshop 2007, VDE-Verlag, 2007 

2006

  • S. Steinhorst, A. Jesser, L. Hedrich. "Advanced Property Specification for Model Checking of Analog Systems," Analog'06 (9. ITG/GMM-Fachtagung), September 2006, pp. 63-68. 
  • X. Wang, L. Hedrich, "Hierarchical Exploration and Selection of Transistor-Topologies for Analog Circuit Design", IEEE International Symposium on Circuits and Systems (ISCAS), May 2006. 
  • A. Jesser, M. Wedler, L. Hedrich, W. Kunz, "A case study on applying bounded model checking to analog circuit verification" 9. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Februar 2006, pp. 106-113. 
  • R. Klausen, E. Barke, L. Hedrich, "Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen" 9. ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Februar 2006, pp. 122-131. 
  • X. Wang, L. Hedrich, "An Approach to Topology Synthesis of Analog Circuits Using Hierarchical Blocks and Symbolic Analysis", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2006

2005

  • J. Oehmen, L. Hedrich, M. Olbrich, E. Barke, "A Methodology for Modeling Lateral Parasitic Transistors in Smart Power ICs," 2005 IEEE International Behavioral Modeling and Simulation Conference, September 2005, pp. 19-24. 
  • D. Grabowski, D. Platte, L. Hedrich, E. Barke, “Time Constrained Verification of Analog Circuits using Model-Checking Algorithms“, Electronic Notes in Theoretical Computer Science (ENTCS): Vol. 153, No 3, Proceedings of the First Workshop on Formal Verification of Analog Circuits (FAC 2005), April 2005, pp. 37-52 
  • D. Platte, D. Grabowski, L. Hedrich, E. Barke, "Verifikation von Zeitbedingungen analoger Schaltungen durch Model-Checking-Verfahren," Analog 2005: 8. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, March 2005, pp. 159-164. 
  • R. Klausen, L. Hedrich, E. Barke, "Äquivalenz-Vergleich nichtlinearer analoger MIMO-Systeme mit automatischer Schrittweitensteuerung," Analog 2005: 8. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, March 2005, pp. 183-188. 
  • Volodymyr Burkhay, Sebastian Breutmann, Lars Hedrich, Erich Barke, "Symbolische Analyse nichtlinearer analoger Schaltungen mit Hilfe Branch-and-Bound-optimierter Vereinfachung," ANALOG'05 (8. GMM/ITG-Diskussionssitzung), March 2005, pp. 253-258.

2004

  • L. Näthke, V. Burkhay, L. Hedrich, E. Barke, "Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits based on Nonlinear Symbolic Techniques", DATE 2004, February 2004

2003

  • A. Lemke, L. Hedrich, E. Barke, "Dimensionierung analoger Schaltungen mit formalen Methoden," 7. ITG/GMM-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, September 2003, pp. 135-140.

2002

  • Andreas Lemke, Lars Hedrich, Erich Barke, "Analog Circuit Sizing Based on Formal Methods Using Affine Arithmetic," ICCAD 2002, November 2002, pp. 486-489. 
  • W. Hartong, L. Hedrich, E. Barke, "Model Checking Algorithms for Analog Verification," DAC 2002, July 2002. 
  • W. Hartong, L. Hedrich, E. Barke, "On Discret Modeling and Model Checking for Nonlinear Analog Systems," CAV 2002: Conference on Computer-Aided Verification, July 2002. 
  • Lutz Näthke, Lars Hedrich, Erich Barke, "Betrachtungen zur Simulationsgeschwindigkeit von Verhaltensmodellen nichtlinearer integrierter Analogschaltungen," Analog 2002, May 2002, pp. 107-112. 
  • R. Popp, J. Oehmen, L. Hedrich, E. Barke, ""Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits"," DATE2002: 5th Design Automation and Test in Europe, March 2002, pp. 274-278. 
  • W. Hartong, L. Hedrich, E. Barke, "An Approach to Model Checking for Nonlinear Analog Systems," Date 2002, March 2002, pp. 1080-1080.

2001

  • M. Olbrich, R. Popp, L. Näthke, L. Hedrich, E. Barke, "A Combined Structural and Symbolic Method for Automatic Behavioral Modeling of Nonlinear Analog Circuits," Proceedings of the 15th European Conference on Circuit Theory and Design (ECCTD 01), August 2001, pp. II-229-232. 
  • L. Näthke, R. Popp, L. Hedrich, E. Barke, "Automatic Analog Behavioral Model Generation," University Booth DATE2001: 4th Design Automation and Test in Europe, March 2001

2000

  • H. Brocke, L. Hedrich, R. Klausen, E. Barke, "Current Density Calculation of Integrated Circuit Interconnect," MICRO.tec 2000 Proceedings Volume 2, September 2000, pp. 77-81. 
  • R. Steiner, L. Dörrer, M. Punzenberger, L. Hedrich, W. Hartong, "Design Story of Low-Voltage and Low-Power Converter and Filter Structures for Wireless Systems," Proc. of the 3rd International Workshop of the European Low Power Initiative for Electronic System Design (ESDLPD 2000), July 2000, pp. 177-210. 
  • T. Adler, H. Brocke, L. Hedrich, E. Barke, "A Current Driven Routing and Verification Methodology for Analog Applications," DAC 2000: 37th Design Automation Conference, June 2000, pp. 385-389. 

1999

  • L. Näthke, R. Popp, L. Hedrich, E. Barke, "Using Term Ordering to Improve Symbolic Behavioral Model Generation of Nonlinear Analog Circuits," ECCTD99: European Conference on Circuit Theory and Design, September 1999, pp. 74-77. 
  • T. Wichmann, R. Popp, W. Hartong, L. Hedrich, "On the Simplification of Nonlinear DAE Systems in Analog Circuit Design," Computer Algebra in Scientific Computing/CASC'99, May 1999, pp. 485-499. 
  • F. Shaikh-Brocke, L. Hedrich, T. Adler, E. Barke, M. Laage, A. Stürmer, C. Rödel, "Berechnung der Stromdichten des Leitbahnsystems integrierter Schaltungen," Analog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, February 1999, pp. 52-53. 
  • W. Hartong, L. Hedrich, E. Barke, "Ein Ansatz zur formalen Verifikation nichtlinearer statischer Analogschaltungen mit Parametertoleranzen," Analog 99: 5. GMM/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden, February 1999, pp. 93-94.

1998

  • L. Hedrich, E. Barke, "A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances," DATE 98: Design, Automation and Test in Europe, February 1998. 
  • R. Popp, W. Hartong, L. Hedrich, E. Barke, "Error Estimation on Symbolic Behavioral Models of Nonlinear Analog Circuits," SMACD 1998: 5th International Conference on Symbolic Methods and Applications to Circuits Design, January 1998.

1996

  • C. Borchers, L. Hedrich, E. Barke, "Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits," DAC 96: 33rd Design Automation Conference, June 1996, pp. 236-239.

1995

  • L. Hedrich, E. Barke, "A Formal Approach to Nonlinear Analog Circuit Verification," ICCAD 95: Int. Conference on Computer Aided Design, November 1995, pp. 123-127. 
  • L. Hedrich, E. Barke, "Ein Verfahren zur Verifikation nichtlinearer analoger Schaltungen," 2. ITG-Diskussionssitzung Neue Anwendungen theoretischer Konzepte in der Elektrotechnik, April 1995, pp. 145-147.