Safety critical systems like autonomous driving or medical devices demand for powerful verification methodologies.Formal verification offers this opportunity. However for analog circuits and systems formal verification suffers from complexity and nonlinearity of underlying equations in transistor models. Vera is a in-house tool used for equivalence checking and thus is a step to concur the verification task. The main concept of the algorithm lies in the sampling done in the state space. Using this sampling algorithm for one circuit only,  has shown how to accurate build behavioral models from the sampled state space thus enhancing design, simulation and validation routines.
This thesis aims to build accurate nonlinear functions from a sampled state space using interpolation methods.
In the mathematical field, interpolation is a method used to build descriptive functions using sampled data points. using the sampled state space and the eigenvalues and eigenvectors at each point in the state space the following tasks should be archived.