• Georg Gläser, Martin Grabmann, Gerrit Kropp and Andreas Fürtig :"There is a limit to everything: Automating AMS operating condition check generation on system-level", Integration, Elsevier, 2018 [LINK]

  • Philipp Tertel, and Lars Hedrich. "Real-time emulation of block-based analog circuits on an FPGA." Integration, Vol. 63, pp. 373-382, Elsevier, 2018. [pdf] [LINK]
  • Markus Meissner, and Lars Hedrich:"FEATS: Framework for Explorative Analog Topology Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.34, No. 2, pp. 213-226, February 2015 [LINK]
  • Julius von Rosen, Felix Salfelder, Lars Hedrich, Benjamin Betting, and Uwe Brinkschulte: "A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture", In Journal "Integration, the VLSI Journal", Elsevier,2015, DOI:10.1016/j.vlsi.2014.04.001. [LINK]
  • M. Ma, L. Hedrich, Ch. Sporrer: "ASDeX: a formal specification for analog circuit enabling a full automated design validation", In journal "Design Automation for Embedded Systems", Springer, 2012, DOI: 10.1007/s10617-012-9088-8. [LINK
  • S. Steinhorst, L. Hedrich. "Advanced methods for equivalence checking of analog circuits with strong nonlinearities", Formal Methods in System Design, Vol. 36, No. 2. (June 2010), pp. 131-147.[BIB
  • A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Advanced Assertion-Based Design for Mixed-Signal Verification", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms, Vol. E91–A, No. 12, pp. 3548-3555, Dezember 2008.
  • Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke: Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electr. Notes Theor. Comput. Sci. 153(3), pp. 37-52 2006